Broadband integrated service digital networks (B-ISDN) will provide end-to-end transport for a wide range of broadband services in a flexible and efficient manner via the asynchronous transfer mode (ATM) technique. The ATM technique provides a standardized and flexible scheme to transport and switch traffic effectively for different services. Due to the natural burstiness of the broadband traffic (e.g. data file transfer and variable bit-rate video communication), congestion control is required to effectively and fairly allocate the shared network resources (e.g., transmission bandwidth and buffer capacity) so that satisfactory quality of service (QOS) to all network users can be provided. Congestion in the ATM network arises when the offered load exceeds the capacity of the network. A suitable set of congestion controls for ATM networks includes admission control, traffic enforcement, queue management, and reactive flow control.
The function of admission control is to decide whether a new virtual channel connection should be admitted to the network (or rejected) based on the knowledge of the current network status (e.g., loading and available resources), the connection's traffic descriptor (including parameters such as average and peak bit rates, and maximum burst lengths), and performance objectives (such as cell loss probability, cell transfer delay, and cell delay variation). A new connection will be admitted only if the QOS can be met and the service quality of calls in progress will not be affected. Several schemes for the call admission control have been proposed.
Reactive flow control alleviates the instantaneous overload condition in the network so that the cell loss in the network is reduced and the users' QOS is maintained. Two reactive flow control schemes have been suggested: backward congestion notification (BCN) and forward congestion indication (FCI). For both schemes the source terminal is, either directly or indirectly, informed by the network to adjust its data rate when the network is congested. However, because of the large product of the transmission bandwidth and the round-trip delay, many cells will still be in transit between the source terminal and the congested node, and may be lost by the time the source terminal receives the congestion information and starts to regulate its traffic flow.
A traffic enforcer, as shown in FIG. 1, monitors (or polices) each virtual connection to ensure that its traffic flow into the network conforms to the traffic descriptor, which could be specified at call setup. If the user's traffic does not conform to the traffic descriptor, some action has to be taken against the violating traffic. For instance, the violating cells could be dropped, temporarily stored in a reshaping buffer, or transmitted to the network anyway, but with the cells tagged with a lower priority. The last option implies that some sort of priority mechanism has to be implemented within the network.
A traffic enforcement scheme that has a buffer to delay and reshape the violating cells is disclosed in the above-noted U.S. patent application entitled "Method and System for Controlling Packet Access to a Packet Switching System." If the buffer is full, some cells are transmitted to the network but are tagged with a lower priority. A novel architecture to implement the traffic enforcer or a traffic shaper at the customer premises is also disclosed. This architecture is capable of performing the traffic enforcement for a large number of virtual channels (e.g., a few thousand) on each input line.
Since a future network node will have to deal with traffic having different requirements, the use of multiple priorities and switch control functions serves as a possibility for distinguishing among different traffic types. A queue manager as shown in FIG. 1 manages the queued cells in a network node in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. By assigning a departure sequence number to every cell, the effect of long-burst traffic on other cells is avoided. An architecture to implement the queue manager using a mechanism called VirtualClock is disclosed in the above-noted U.S. patent application entitled "Method and System for Managing Queued Cells." The architecture has the capability to support thousands of priority levels.
An object of the present invention is to provide a sequencer chip device for use in a system which performs traffic enforcement for a large number of virtual channels on each input line.
Another object of the present invention is to provide a sequencer chip device for use in a system which manages queued cells in a network node in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full and any interference between same priority cells is prevented.
In carrying out the above objects and other objects of the present invention, a sequencer chip device for use in a broadband integrated service digital network is provided wherein users' traffic in the form of ATM cells is controlled. The device includes a plurality of modules connected in series for receiving data related to the ATM cells and means for broadcasting new data related to a new ATM cell received by the device to each of the modules in a write-in mode of the chip device. Each of the modules includes memory means for storing prior data related to a previously received ATM cell, and means for comparing the new data with the prior data to obtain a comparison signal. Each of the modules also includes controller means coupled to its respective memory means and means for comparing for alternately retaining the stored prior data or replacing the stored prior data with the new data or with prior data from an immediately adjacent memory means based on the comparison signal of its means for comparing and the comparison signal of the immediately adjacent means for comparing.
Preferably, the device is a single VLSI chip. Also preferably, the chip is a word sorting memory chip.
The above objects and other objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.
FIG. 1 is a block diagram illustrating how users' traffic is controlled at two places in an ATM network;
FIG. 2 is a graph illustrating three different actions to the violated cells: discarding, tagging, and reshaping;
FIG. 3 is a block diagram illustrating a traffic enforcer's architecture;
FIG. 4 is a block diagram illustrating how a new arrival is inserted into the sequencer chip device of the present invention;
FIGS. 5a, 5b and 5c are schematic block diagrams illustrating how departure sequence numbers (DSs) are assigned to arrival cells;
FIG. 6 is a block diagram illustrating the queue manager's architecture;
FIG. 7 is a block diagram of the sequencer ship device;
FIG. 8 is a block diagram schematically illustrating the interconnection signals of two cascaded sequencer chip devices;
FIG. 9 are timing diagrams of initialization, write-in, and read-out operations of the device;
FIG. 10 is a circuit diagram of a controller of the device;
FIG. 11 is a circuit diagram of a subtractor of the device;
FIGS. 12a, 12b and 12c illustrate three different circuits for a static, D-type flip-flop of the device; and
FIG. 13 is a test circuit for comparing the three different DFFs' speed.